As semiconductor technology progresses, the resistance of polysilicon lines used to form gates of MOSFET transistors becomes unacceptably high. As a result, silicide (such as titanium silicide) is commonly added to the polysilicon lines to reduce the resistance. In a self-aligned (salicide) process, a layer of titanium is deposited over the structure and reacted in a nitrogen ambient at temperatures on the order of 650-750.degree. C. The titanium layer reacts with the silicon of the polysilicon lines and/or the source/drain regions to form a titanium-silicide layer and with the nitrogen ambient to form a titanium nitride layer. The titanium nitride and any unreacted titanium are then removed. An anneal on the order of 800-900.degree. C. is then used to lower the sheet resistance and stabilize the titanium silicide phase (i.e., transform C49 phase titanium silicide to a lower resistance C54 phase). The lower resistance C54 phase of titanium silicide is preferred over the higher resistance C49 phase. Unfortunately, as device geometries shrink, it becomes more and more difficult to transform the C49 phase to the C54 phase. Therefore, it is very difficult to form a low sheet resistance titanium salicide for sub-0.25 .mu.m CMOS technology. One proposed method to overcome this limitation is to use a pre-amorphization implant (PAI) prior to titanium deposition. The implant reduces the narrow linewidth effect and sheet resistances can be maintained below 10 ohms/[ ] for 0.2 .mu.m N-type polysilicon gate linewidths. However, when the polysilicon gate linewidth drops below 0.16 .mu.m, current silicide processes with a PAI result in many individual instances wherein the resistance is above 10 ohms/[ ]. Accordingly, there is a need to extend the usefulness of titanium-silicide to the sub-0.2 .mu.m technologies.